Digital processing circuits require one or more clock signals to function. Clock signals are typically derived from a fundamental clock signal provided by a crystal oscillator. For example, a clock signal having a frequency lower than that of the fundamental clock signal can be obtained by dividing the fundamental clock signal by an appropriate amount. In circuits where multiple clock signals are required, these can be obtained in an efficient manner by chaining together a set of frequency dividers. For example, if the fundamental frequency is fo, frequencies fo/2 and fo/4 may be obtained by applying the fundamental clock signal to a divide-by-2 circuit and applying the output of that circuit to a further divide-by-2 circuit.
FIG. 1 illustrates schematically a typical divide-by-6 circuit which is based on a Johnson ring. The circuit comprises a chain of three D-type flip flops. Each flip flop comprises a pair of D-type latches (not illustrated in the Figure), where the first member of each pair receives the clock signal to be divided, whilst the second member of each pair receives the inverted clock signal. This clocking arrangement results in the first member of each latch pair changing its state on the rising edge of a clock pulse and the second member of each pair changing its state on the falling edge, thus ensuring that the input to a given latch is in a steady state when that latch is clocked. The inverted output from the final flip flop fed back as the D input to the first latch. This arrangement results in sequences of 0's and 1's being clocked through the chain in turn. The output of the circuit is provided either by Q or /Q of the final flip flop.
A problem arises where it is required to obtain a clock signal which is an odd number division of the fundamental clock signal frequency, i.e. where we need a divide-by-N circuit where N is an odd number. FIG. 2 illustrates schematically a divide-by-5 circuit (based upon the divide-by-6 circuit of FIG. 1). The circuit of FIG. 1 is modified by the inclusion of an AND gate (“&”) which receives at its inputs the inverted outputs of the second and third flip flops. The output of the AND gate provides the input to the first flip flop. This configuration causes a “0” to be clocked into the input of the first flip flop, one clock pulse earlier than would otherwise have happened. The pulse sequence through the counter is therefore three “0”s followed by two “1”s. However, it will be appreciated that the duty cycle of this circuit is 40%. This is not suitable for many applications.
For the purpose of illustration, FIG. 3 show the state tables for the divide-by-6 and divide-by-5 counters of FIGS. 1 and 2. FIG. 4 shows the corresponding state diagrams.